Currently, for inverter circuits formed by connecting a high-side switching element and a low-side switching element in series, a time period (dead time) can be set during which both the switching elements are off. This is to prevent the two switching elements from being simultaneously turned on (or short-circuited). Setting the dead time causes distortion of output current of the inverter circuit.
A technique to reduce distortion of output voltage is described in Patent Document 1 (identified below) in which a PWM converter adds a compensation signal to a voltage command value to compensate for an error voltage caused by the dead time. In the technique described in Patent Document 1, a current phase is determined from a power supply voltage phase detection value, and dead-time compensation is performed in accordance with the determined current phase.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 9-154280.
However, voltage and current have a phase difference that constantly varies, and it is difficult to always accurately detect a phase current. With the technique described in Patent Document 1, therefore, it is difficult to appropriately perform dead-time compensation in accordance with current distortion that occurs in real time. Alternating current may be directly detected to adjust a current phase during execution of a fast Fourier transform (FFT), but this is less realistic because a large amount of computation is required and a heavy load is placed on the processor.